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FINAL
AM28F010A
1 Megabit (128 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
s High performance -- Access times as fast as 70 ns s CMOS low power consumption -- 30 mA maximum active current -- 100 A maximum standby current -- No data retention power consumption s Compatible with JEDEC-standard byte-wide 32-pin EPROM pinouts -- 32-pin PDIP -- 32-pin PLCC -- 32-pin TSOP s 100,000 write/erase cycles minimum s Write and erase voltage 12.0 V 5% s Latch-up protected to 100 mA from -1 V to VCC +1 V s Embedded Erase Electrical Bulk Chip Erase -- 5 seconds typical chip erase, including pre-programming s Embedded Program -- 14 s typical byte program, including time-out -- 4 seconds typical chip program s Command register architecture for microprocessor/microcontroller compatible write interface s On-chip address and data latches s Advanced CMOS flash memory technology -- Low cost single transistor memory cell s Embedded algorithms for completely self-timed write/erase operations
GENERAL DESCRIPTION
The AM28F010A is a 1 Megabit Flash memory organized as 128 Kbytes of 8 bits each. AMD's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The AM28F010A is packaged in 32-pin PDIP, PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The AM28F010A is erased when shipped from the factory. The standard AM28F010A offers access times of as fast as 70 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention, the device has separate chip enable (CE#) and output enable (OE#) controls. AMD's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The AM28F010A uses a command register to manage this functionality. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maximum EPROM compatibility. T h e A m 28 F 0 10 A i s com p a tibl e w i th th e A M D Am28F256A, Am28F512A, and Am28F020A Flash memories. All devices in the Am28Fxxx family follow the JEDEC 32-pin pinout standard. In addition, all devices
Publication# 16778 Rev: D Amendment/+2 Issue Date: May 1998
within this family that offer Embedded Algorithms use the same command set. This offers designers the flexibility to retain the same device footprint and command set, at any density between 256 Kbits and 2 Mbits. AMD's Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The AMD cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The AM28F010A uses a 12.05% VPP input to perform the erase and programming functions. The highest degree of latch-up protection is achieved with AMD's proprietary non-epi process. Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1 V to VCC +1 V. AMD's Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The AM28F010A electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.
Embedded Program
The AM28F010A is byte programmable using the Embedded Program algorithm, which does not require the system to time-out or verify the data programmed. The typical room temperature programming time of this device is two seconds.
Embedded Erase
The entire device is bulk erased using the Embedded Erase algorithm, which automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internal to the device. Typical erasure time at room temperature is five seconds, including preprogramming.
Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms
AM28F010A with Embedded Algorithms Embedded Programming Algorithm vs. Flashrite Programming Algorithm AMD's Embedded Programming algorithm requires the user to only write a program set-up command and a program command (program data and address). The device automatically times the programming pulse width, verifies the programming, and counts the number of sequences. A status bit, Data# Polling, provides the user with the programming operation status. Am28F010 using AMD Flashrite and Flasherase Algorithms The Flashrite Programming algorithm requires the user to write a program set-up command, a program command, (program data and address), and a program verify command, followed by a read and compare operation. The user is required to time the programming pulse width in order to issue the program verify command. An integrated stop timer prevents any possibility of overprogramming. Upon completion of this sequence, the data is read back from the device and compared by the user with the data intended to be written; if there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 25 times. The Flasherase Erase algorithm requires the device to be completely programmed prior to executing an erase command. To invoke the erase operation, the user writes an erase set-up command, an erase command, and an erase verify command. The user is required to time the erase pulse width in order to issue the erase verify command. An integrated stop timer prevents any possibility of overerasure. Upon completion of this sequence, the data is read back from the device and compared by the user with erased data. If there is not a match, the sequence is repeated until there is a match or the sequence has been repeated 1,000 times.
Embedded Erase Algorithm vs. Flasherase Erase Algorithm
AMD's Embedded Erase algorithm requires the user to only write an erase setup command and erase command. The device automatically pre-programs and verifies the entire array. The device then automatically times the erase pulse width, verifies the erase operation, and counts the number of sequences. A status bit, Data# Polling, provides the user with the erase operation status.
Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine, which controls the erase and programming circuitry. During write cycles, the command register internally latches addresses and data needed for the programming and erase operations. For system design simplification, the AM28F010A is designed to support either WE# or CE# controlled writes. During a system write
cycle, addresses are latched on the falling edge of WE# or CE#, whichever occurs last. Data is latched on the rising edge of WE# or CE#, whichever occurs first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.
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AM28F010A
PRODUCT SELECTOR GUIDE
Family Part Number Speed Options (VCC = 5.0 V 10%) Max Access Time (ns) CE# (E#) Access (ns) OE# (G#) Access (ns) -70 70 70 35 -90 90 90 35 AM28F010A -120 120 120 50 -150 150 150 55 -200 200 200 55
BLOCK DIAGRAM
DQ0-DQ7
VCC VSS VPP
Erase Voltage Switch Input/Output Buffers
To Array WE# State Control Command Register CE# OE# Program Voltage Switch
Chip Enable Output Enable Logic Data Latch
Embedded Algorithms Y-Decoder Address Latch Program/Erase Pulse Timer Y-Gating
Low VCC Detector
X-Decoder
1,048,576 Bit Cell Matrix
A0-A16
16778D-1
AM28F010A
3
CONNECTION DIAGRAMS
PDIP VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE# (W#) PLCC
WE# (W#)
VCC
A12
A15
A16
VPP
NC A14 A13 A8 A9 A11 OE# (G#) A10 CE# (E#) DQ7 DQ6 DQ5 DQ4 DQ3
4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13
3
2
1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE (G) A10 CE# (E#) DQ7
14 15 16 17 18 19 20 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 VSS
16778D-2
NC
16778D-3
Note: Pin 1 is marked for orientation.
4
AM28F010A
CONNECTION DIAGRAMS (continued)
A11 A9 A8 A13 A14 NC WE# VCC VPP A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin TSOP--Standard Pinout
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3
OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32-Pin TSOP--Reverse Pinout
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A11 A9 A8 A13 A14 NC WE# VCC VPP A16 A15 A12 A7 A6 A5 A4
16778D-4
LOGIC SYMBOL
17 A0-A16 DQ0-DQ7 CE# (E#) OE# (G#) WE# (W#) 8
16778D-5
AM28F010A
5
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The ordering number (Valid Combination) is formed by a combination of the following: AM28F010A -70 J C B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In Contact an AMD representative for more information. TEMPERATURE RANGE C = Commercial (0C to +70C) I = Industrial (-40C to +85C) E = Extended (-55C to +125C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION AM28F010A 1 Megabit (128 K x 8-Bit) CMOS Flash Memory with Embedded Algorithms
Valid Combinations AM28F010A-70 AM28F010A-90 AM28F010A-120 AM28F010A-150 AM28F010A-200 PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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AM28F010A
PIN DESCRIPTION A0-A16
Address Inputs for memory locations. Internal latches hold addresses during write cycles.
cycles. Output Enable is high during command sequencing and program/erase operations.
VCC
Power supply for device operation. (5.0 V 5% or 10%)
CE# (E#)
Chip Enable active low input activates the chip's control logic and input buffers. Chip Enable high will deselect the device and operates the chip in stand-by mode.
VPP
Program voltage input. VPP must be at high voltage in order to write to the command register. The command register controls all functions required to alter the memory array contents. Memory contents cannot be altered when VPP VCC +2 V.
DQ0-DQ7
Data Inputs during memory write cycles. Internal latches hold data during write cycles. Data Outputs during memory read cycles.
VSS
Ground
NC
No Connect--corresponding pin is not connected internally to the die.
WE# (W#)
Write Enable active low input controls the write function of the command register to the memory array. The target address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits writing to the device.
OE# (G#)
Output Enable active low input gates the outputs of the device through the data buffers during memory read
AM28F010A
7
BASIC PRINCIPLES
This section contains descriptions about the device read, erase, and program operations, and write operation status of the Am29FxxxA, 12.0 volt family of Flash devices. References to some tables or figures may be given in generic form, such as "Command Definitions table", rather than "Table 1". Refer to the corresponding data sheet for the actual table or figure. The Am28FxxxA family uses 100% TTL-level control inputs to manage the command register. Erase and reprogramming operations use a fixed 12.0 V 5% high voltage input.
Embedded Programming Algorithm
AMD now makes programming extremely simple and reliable. The Embedded Programming algorithm requires the user to only write a program setup command and a program command. The device automatically times the programming pulse width, provides the program verify and counts the number of sequences. A status bit, Data# Polling, provides feedback to the user as to the status of the programming operation.
DATA PROTECTION
The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. The device powers up in its read only state. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from V CC power-up and power-down transitions or system noise.
Read Only Memory
Without high VPP voltage, the device functions as a read only memory and operates like a standard EPROM. The control inputs still manage traditional read, standby, output disable, and Auto select modes.
Command Register
The command register is enabled only when high voltage is applied to the VPP pin. The erase and reprogramming operations are only accessed via the register. In addition, two-cycle commands are required for erase and reprogramming operations. The traditional read, standby, output disable, and Auto select modes are available via the register. The device's command register is written using standard microprocessor write timings. The register controls an internal state machine that manages all device operations. For system design simplification, the device is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occur first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, the device locks out write cycles for VCC < VLKO (see DC characteristics section for voltages). When VCC < VLKO, the command register is disabled, all internal program/erase circuits are disabled, and the device resets to the read mode. The device ignores all writes until VCC > VLKO. The user must ensure that the control pins are in the correct logic state when VCC > VLKO to prevent unintentional writes.
Write Pulse "Glitch" Protection
Noise pulses of less than 10 ns (typical) on OE#, CE# or WE# will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE# = VIL, CE#=VIH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one.
OVERVIEW OF ERASE/PROGRAM OPERATIONS Embedded Erase Algorithm
AMD now makes erasure extremely simple and reliable. The Embedded Erase algorithm requires the user to only write an erase setup command and erase command. The device will automatically pre-program and verify the entire array. The device automatically times the erase pulse width, provides the erase verify and counts the number of sequences. A status bit, Data# Polling, provides feedback to the user as to the status of the erase operation.
Power-Up Write Inhibit
Power-up of the device with WE# = CE# = VIL and OE# = V IH will not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
8
AM28F010A
FUNCTIONAL DESCRIPTION Description Of User Modes
Table 1.
Operation Read Standby Output Disable Read-Only Auto-select Manufacturer Code (Note 2) Auto-select Device Code (Note 2) Read
AM28F010A Device Bus Operations (Notes 7 and 8)
CE# (E#) VIL VIH VIL VIL VIL VIL VIH VIL VIL OE# (G#) VIL X VIH VIL VIL VIL X VIH VIH WE# (W#) X X VIH VIH VIH VIH X VIH VIL VPP (Note 1) VPPL VPPL VPPL VPPL VPPL VPPH VPPH VPPH VPPH A0 A0 X X VIL VIH A0 A9 A9 X X VID (Note 3) VID (Note 3) A9 I/O DOUT HIGH Z HIGH Z CODE (01h) CODE (A2h) DOUT (Note 4) HIGH Z HIGH Z DIN (Note 6)
Standby (Note 5) Read/Write Output Disable Write
X X A0
X X A9
Legend: X = Don't care, where Don't Care is either VIL or VIH levels. VPPL = VPP < VCC + 2 V. See DC Characteristics for voltage levels of VPPH. 0 V < An < VCC + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9). Notes: 1. VPPL may be grounded, connected with a resistor to ground, or < VCC + 2.0 V. VPPH is the programming voltage specified for the device. Refer to the DC characteristics. When VPP = VPPL, memory contents can be read but not written or erased. 2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2. 3. 11.5 < VID < 13.0 V. Minimum VID rise time and fall time (between 0 and VID voltages) is 500 ns. 4. Read operation with VPP = VPPH may access array data or the Auto select codes. 5. With VPP at high voltage, the standby current is ICC + IPP (standby). 6. Refer to Table 3 for valid DIN during a write operation. 7. All inputs are Don't Care unless otherwise stated, where Don't Care is either VIL or VIH levels. In the Auto select mode all addresses except A9 and A0 must be held at VIL. 8. If VCC 1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F256 has a VPP rise time and fall time specification of 500 ns minimum.
AM28F010A
9
READ-ONLY MODE
When VPP is less than VCC + 2 V, the command register is inactive. The device can either read array or autoselect data, or be standby mode.
Output Disable
Output from the device is disabled when OE# is at a logic high level. When disabled, output pins are in a high impedance state.
Read
The device functions as a read only memory when VPP < VCC + 2 V. The device has two control functions. Both must be satisfied in order to output data. CE# controls power to the device. This pin should be used for specific device selection. OE# controls the device outputs and should be used to gate data to the output pins if a device is selected. Address access time tACC is equal to the delay from stable addresses to valid output data. The chip enable access time tCE is the delay from stable addresses and stable CE# to valid data at the output pins. The output enable access time is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable at least tACC - tOE).
Auto Select
Flash memories can be programmed in-system or in a standard PROM programmer. The device may be soldered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the board. The Auto select mode allows the reading out of a binary code from the device that will identify its manufacturer and type. This mode is intended for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.
Standby Mode
The device has two standby modes. The CMOS standby mode (CE# input held at VCC 0.5 V), consumes less than 100 A of current. TTL standby mode (CE# is held at VIH) reduces the current requirements to less than 1 mA. When in the standby mode the outputs are in a high impedance state, independent of the OE# input. If the device is deselected during erasure, programming, or program/erase verification, the device will draw active current until the operation is terminated.
Programming In a PROM Programmer
To activate this mode, the programming equipment must force VID (11.5 V to 13.0 V) on address A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All other address lines must be held at VIL, and V PP must be less than or equal to VCC + 2.0 V while using this Auto select mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the device the two bytes are given in the table 2 of the device data sheet. All identifiers for manufacturer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit.
Table 2.
Type Manufacturer Code Device Code
AM28F010A Auto Select Code
A0 VIL VIH Code (HEX) 01 A2
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AM28F010A
ERASE, PROGRAM, AND READ MODE
When VPP is equal to 12.0 V 5%, the command register is active. All functions are available. That is, the device can program, erase, read array or autoselect data, or be standby mode. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Command Definitions
The contents of the command register default to 00h (Read Mode) in the absence of high voltage applied to the V PP pin. The device operates as a read only memory. High voltage on the V PP pin enables the command register. Device operations are selected by writing specific data codes into the command register. Table 3 in the device data sheet defines these register commands.
Write Operations
High voltage must be applied to the VPP pin in order to activate the command register. Data written to the register serves as input to the internal state machine. The output of the state machine determines the operational function of the device. The command register does not occupy an addressable memory location. The register is a latch that stores the command, along with the address and data information needed to execute the command. The register is written by bringing WE# and CE# to VIL, while OE# is at VIH. Addresses are latched on the falling edge of WE#, while data is latched on the rising edge of the WE# pulse. Standard microprocessor write timings are used. The device requires the OE# pin to be VIH for write operations. This condition eliminates the possibility for bus contention during programming operations. In order to write, OE# must be VIH, and CE# and WE# must be VIL. If any pin is not in the correct state a write command will not be executed.
Read Command
Memory contents can be accessed via the read command when VPP is high. To read from the device, write 00h into the command register. Standard microprocessor read cycles access data from the memory. The device will remain in the read mode until the command register contents are altered. The command register defaults to 00h (read mode) upon VPP power-up. The 00h (Read Mode) register default helps ensure that inadvertent alteration of the memory contents does not occur during the VPP power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
Table 3.
AM28F010A Command Definitions
First Bus Cycle Second Bus Cycle Data (Note 3) 00h/FFh 80h or 90h 30h 10h or 50h 00h/FFh Operation (Note 1) Read Read Write Write Write Address (Note 2) RA 00h/01h X PA X Data (Note 3) RD 01h/A2h 30h PD 00h/FFh
Command Read Memory (Note 4) Read Auto select Embedded Erase Set-up/ Embedded Erase Embedded Program Set-up/ Embedded Program Reset (Note 4)
Operation (Note 1) Write Write Write Write Write
Address (Note 2) X X X X X
Notes: 1. Bus operations are defined in Table 1. 2. RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# pulse. X = Don't care. 3. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latched on the rising edge of WE#. 4. Please reference Reset Command section.
AM28F010A
11
FLASH MEMORY PROGRAM/ERASE OPERATIONS Embedded Erase Algorithm
The automatic chip erase does not require the device to be entirely pre-programmed prior to executing the Embedded set-up erase command and Embedded erase command. Upon executing the Embedded erase command the device automatically will program and verify the entire memory for an all zero data pattern. The system is not required to provide any controls or timing during these operations. When the device is automatically verified to contain an all zero pattern, a self-timed chip erase and verify begin. The erase and verify operation are complete when the data on DQ7 is "1" (see Write Operation Status section) atwhich time the device returns to Read mode. The system is not required to provide any control or timing during these operations. When using the Embedded Erase algorithm, the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). The margin voltages are internally generated in the same manner as when the standard erase verify command is used. The Embedded Erase Set-Up command is a command only operation that stages the device for automatic electrical erasure of all bytes in the array. Embedded Erase Setup is performed by writing 30h to the command register. To commence automatic chip erase, the command 30h must be written again to the command register. The automatic erase begins on the rising edge of the WE and terminates when the data on DQ7 is "1" (see Write Operation Status section) at which time the device returns to Read mode. Figure 1 and Table 4 illustrate the Embedded Erase algorithm, a typical command string and bus operation.
START
Apply VPPH
Write Embedded Erase Setup Command
Write Embedded Erase Command
Data# Poll from Device
Erasure Completed
16778D-6
Figure 1. Table 4.
Bus Operations Standby Command
Embedded Erase Algorithm Embedded Erase Algorithm
Comments Wait for VPP Ramp to VPPH (see Note)
Embedded Erase Setup Command Write Embedded Erase Command Read Standby Read
Data = 30h Data = 30h Data# Polling to Verify Erasure Compare Output to FFh Available for Read Operations
Note: See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. Refer to Functional Description.
12
AM28F010A
Embedded Programming Algorithm
The Embedded Program Setup is a command only operation that stages the device for automatic programming. Embedded Program Setup is performed by writing 10h or 50h to the command register. Once the Embedded Setup Program operation is performed, the next WE# pulse causes a transition to an active programming operation. Addresses are latched on the falling edge of CE# or WE# pulse, whichever happens later. Data is latched on the rising edge of WE# or CE#, whichever happens first. The rising edge
of WE# also begins the programming operation. The system is not required to provide further controls or timings. The device will automatically provide an adequate internally generated program pulse and verify margin. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit (see Write Operation Status section) at which time the device returns to Read mode. Figure 2 and Table 5 illustrate the Embedded Program algorithm, a typical command string, and bus operation.
START
Apply VPPH
Write Embedded Setup Program Command
Write Embedded Program Command (A/D)
Data# Poll Device
Increment Address
No
Last Address Yes
Programming Completed
16778D-7
Figure 2. Table 5.
Bus Operations Standby Write Write Read Read
Embedded Programming Algorithm Embedded Programming Algorithm
Comments Wait for VPP Ramp to VPPH (see Note)
Command
Embedded Program Setup Command Embedded Program Command
Data = 10h or 50h Valid Address/Data Data# Polling to Verify Completion Available for Read Operations
Note: See AC and DC Characteristics for values of VPP parameters. The VPP power supply can be hard-wired to the device or switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. Refer to Functional Description. Device is either powered-down, erase inhibit or program inhibit.
AM28F010A
13
Write Operation Status
Data Polling--DQ7 The device features Data# Polling as a method to indicate to the host system that the Embedded algorithms are either in progress or completed. While the Embedded Programming algorithm is in operation, an attempt to read the device at a valid address will produce the complement of expected Valid data on DQ7. Upon completion of the Embedded Program algorithm an attempt to read the device at a valid address will produce Valid data on DQ7. The Data# Polling feature is valid after the rising edge of the second WE# pulse of the two write pulse sequence.
While the Embedded Erase algorithm is in operation, DQ7 will read "0" until the erase operation is completed. Upon completion of the erase operation, the data on DQ7 will read "1." The Data# Polling feature is valid after the rising edge of the second WE# pulse of the two Write pulse sequence. The Data# Polling feature is only active during Embedded Programming or erase algorithms. See Figures 3 and 4 for the Data# Polling timing specifications and diagrams. Data# Polling is the standard method to check the write operation status, however, an alternative method is available using Toggle Bit.
START
Read Byte (DQ0-DQ7) Addr = VA
VA = Byte address for programming = XXXXh during chip erase
DQ7 = Data ? No No
Yes
DQ5 = 1 ? Yes Read Byte (DQ0-DQ7) Addr = VA
DQ7 = Data ? No Fail
Yes
Pass
16778D-8
Note: DQ7 is rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5 or after DQ5.
Figure 3.
Data# Polling Algorithm
14
AM28F010A
tCH CE# tOE OE# tOEH tDF
WE#
tCE tOH * DQ7 DQ7# DQ7 = Valid Data High Z
tWHWH 3 or 4 DQ0-DQ6 DQ0-DQ6 = Invalid
DQ0-DQ7 Valid Data
16778D-9
*DQ7 = Valid Data (The device has completed the Embedded operation.)
Figure 4.
AC Waveforms for Data# Polling during Embedded Algorithm Operations
AM28F010A
15
Toggle Bit--DQ6 The device also features a "Toggle Bit" as a method to indicate to the host system that the Embedded algorithms are either in progress or completed. Successive attempts to read data from the device at a valid address, while the Embedded Program algorithm is in progress, or at any address while the Embedded Erase algorithm is in progress, will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase algorithm is completed, DQ6 will stop
toggling to indicate the completion of either Embedded operation. Only on the next read cycle will valid data be obtained. The toggle bit is valid after the rising edge of the first WE# pulse of the two write pulse sequence, unlike Data# Polling which is valid after the rising edge of the second WE# pulse. This feature allows the user to determine if the device is partially through the two write pulse sequence. See Figures 5 and 6 for the Toggle Bit timing specifications and diagrams.
START
Read Byte (DQ0-DQ7) Addr = VA
VA = Byte address for programming = XXXXh during chip erase
DQ6 = Toggle ? Yes No DQ5 = 1 ? Yes Read Byte (DQ0-DQ7) Addr = VA
No
DQ6 = Toggle ? Yes Fail
No
Pass
16778D-10
Note: DQ6 is rechecked even if DQ5 = "1" because DQ6 may stop toggling at the same time as DQ5 changing to "1".
Figure 5.
Toggle Bit Algorithm
16
AM28F010A
CE# tOEH WE#
OE#
* Data DQ0-DQ7 DQ6 = DQ6 = tOE
16778D-11
DQ6 Stop Toggling
DQ0-DQ7 Valid
Note: *DQ6 stops toggling (The device has completed the Embedded operation.)
Figure 6.
AC Waveforms for Toggle Bit during Embedded Algorithm Operations
DQ5
Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits. This is a failure condition and the device may not be used again (internal pulse count exceeded). Under these conditions DQ5 will produce a "1." The program or erase cycle was not successfully completed. Data# Polling is the only operating function of the device under this condition. The CE# circuit will partially power down the device under these conditions (to approximately 2 mA). The OE# and WE# pins will control the output disable functions as described in the Command Definitions table in the corresponding device data sheet. Parallel Device Erasure The Embedded Erase algorithm greatly simplifies parallel device erasure. Since the erase process is internal to the device, a single erase command can be given to multiple devices concurrently. By implementing a parallel erase algorithm, total erase time may be minimized. Note that the Flash memories may erase at different rates. If this is the case, when a device is completely erased, use a masking code to prevent further erasure (over-erasure). The other devices will continue to erase until verified. The masking code applied could be the read command (00h).
Power-Up/Power-Down Sequence The device powers-up in the Read only mode. Power supply sequencing is not required. Note that if VCC 1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 Volts. Also, the device has a rise VPP rise time and fall time specification of 500 ns minimum. Reset Command The Reset command initializes the Flash memory device to the Read mode. In addition, it also provides the user with a safe method to abort any device operation (including program or erase). The Reset must be written two consecutive times after the Setup Program command (10h or 50h). This will reset the device to the Read mode. Following any other Flash command, write the Reset command once to the device. This will safely abort any previous operation and initialize the device to the Read mode. The Setup Program command (10h or 50h) is the only command that requires a two-sequence reset cycle. The first Reset command is interpreted as program data. However, FFh data is considered as null data during programming operations (memory cells are only programmed from a logical "1" to "0"). The second Reset command safely aborts the programming operation and resets the device to the Read mode. Memory contents are not altered in any case. AM28F010A 17
This detailed information is for your reference. It may prove easier to always issue the Reset command two consecutive times. This eliminates the need to determine if you are in the Setup Program state or not. In-System Programming Considerations Flash memories can be programmed in-system or in a standard PROM programmer. The device may be soldered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the circuit board. Auto Select Command AMD's Flash memories are designed for use in applications where the local CPU alters memory contents. In order to correctly program any Flash memories
in-system, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a generally desired system design practice. The device contains an Auto Select operation to supplement traditional PROM programming methodologies. The operation is initiated by writing 80h or 90h into the command register. Following this command, a read cycle address 0000h retrieves the manufacturer code of 01h (AMD). A read cycle from address 0001h returns the device code (see the Auto Select Code table of the corresponding device data sheet). To terminate the operation, it is necessary to write another valid command, such as Reset (00h or FFh), into the register.
18
AM28F010A
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . -65C to +125C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Voltage with Respect to Ground All pins except A9 and VPP (Note 1) .-2.0 V to +7.0 V VCC (Note 1). . . . . . . . . . . . . . . . . . . .-2.0 V to +7.0 V A9, VPP (Note 2) . . . . . . . . . . . . . . .-2.0 V to +14.0 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. 2. Minimum DC input voltage on pins A9 and VPP is -0.5 V. During voltage transitions, A9 and VPP may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 and VPP is +13.0 V, which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) . . . . . . . . . . .0C to +70C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . .-40C to +85C Extended (E) Devices Ambient Temperature (TA) . . . . . . . .-55C to +125C VCC Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V VPP Voltages Read . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +12.6 V Program, Erase, and Verify . . . . . . +11.4 V to +12.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
AM28F010A
19
MAXIMUM OVERSHOOT
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns
16778D-12
Maximum Negative Input Overshoot
20 ns VCC + 2.0 V VCC + 0.5 V 2.0 V 20 ns 20 ns
16778D-13
Maximum Positive Input Overshoot
20 ns 14.0 V 13.5 V VCC + 0.5 V 20 ns 20 ns
16778D-14
Maximum VPP Overshoot
20
AM28F010A
DC CHARACTERISTICS over operating range unless otherwise specified TTL/NMOS Compatible
Parameter Symbol ILI ILO ICCS ICC1 ICC2 ICC3 IPPS IPP1 Parameter Description Input Leakage Current Output Leakage Current VCC Standby Current VCC Active Read Current VCC Programming Current VCC Erase Current VPP Standby Current VPP Read Current Test Conditions VCC = VCC Max, VIN = VCC or VSS VCC = VCC Max, VOUT = VCC or VSS VCC = VCC Max, CE# = VIH VCC = VCC Max, CE# = VIL, OE# = VIH IOUT = 0 mA, at 6 MHz CE = VIL Programming in Progress (Note 4) CE# = VIL Erasure in Progress (Note 4) VPP = VPPL VPP = VPPH VPP = VPPL VPP = VPPH Programming in Progress (Note 4) VPP = VPPH Erasure in Progress (Note 4) -0.5 2.0 IOL = 5.8 mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min A9 = VID A9 = VID Max, VCC = VCC Max 2.4 11.5 5 0.0 11.4 3.2 3.7 13.0 50 VCC +2.0 12.6 10 10 70 0.2 20 20 20 Min Typ Max 1.0 1.0 1.0 30 30 30 1.0 200 1.0 30 30 0.8 VCC + 0.5 0.45 A Unit A A mA mA mA mA A
IPP2 IPP3 VIL VIH VOL VOH1 VID IID VPPL VPPH VLKO
VPP Programming Current VPP Erase Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage A9 Auto Select Voltage A9 Auto Select Current VPP during Read-Only Operations VPP during Read/Write Operations Low VCC Lock-out Voltage
mA mA V V V V V A V V V
Note: Erase/Program are inhibited when VPP = VPPL
Notes: 1. Caution: The AM28F010A must not be removed from (or inserted into) a socket when VCC or VPP is applied. If VCC 1.0 volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the AM28F010A has a VPP rise time and fall time specification of 500 ns minimum. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 3. Maximum active power usage is the sum of ICC and IPP. 4. Not 100% tested.
AM28F010A
21
DC CHARACTERISTICS CMOS Compatible
Parameter Symbol ILI ILO ICCS ICC1 Parameter Description Input Leakage Current Output Leakage Current VCC Standby Current VCC Active Read Current Test Conditions VCC = VCC Max, VIN = VCC or VSS VCC = VCC Max, VOUT = VCC or VSS VCC = VCC Max, CE# = VCC 0.5 V VCC = VCC Max, CE# = VIL, OE# = VIH IOUT = 0 mA, at 6 MHz CE# = VIL Programming in Progress (Note 4) CE# = VIL Erasure in Progress (Note 4) VPP = VPPL VPP = VPPH VPP = VPPH Programming in Progress (Note 4) VPP = VPPH Erasure in Progress (Note 4) -0.5 0.7 VCC IOL = 5.8 mA, VCC = VCC Min IOH = -2.5 mA, VCC = VCC Min IOH = -100 A, VCC = VCC Min A9 Auto Select Voltage A9 Auto Select Current VPPL during Read-Only Operations VPP during Read/Write Operations Low VCC Lock-out Voltage A9 = VID A9 = VID Max, VCC = VCC Max 0.85 VCC VCC -0.4 11.5 5 0.0 11.4 3.2 3.7 13.0 50 VCC + 2.0 12.6 V A V V V 70 10 10 15 20 Min Typ Max 1.0 1.0 100 30 Unit A A A mA
ICC2 ICC3 IPPS IPP1 IPP2 IPP3 VIL VIH VOL VOH1 VOH2 VID IID VPPL VPPH VLKO
VCC Programming Current VCC Erase Current VPP Standby Current VPP Read Current VPP Programming Current VPP Erase Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
20 20
30 30 1.0 200 30 30 0.8 VCC + 0.5 0.45
mA mA A A mA mA V V V V
Note: Erase/Program are inhibited when VPP = VPPL
Notes: 1. Caution: The AM28F010A must not be removed from (or inserted into) a socket when VCC or VPP is applied. If VCC 1.0 volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the AM28F010A has a VPP rise time and fall time specification of 500 ns minimum. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 3. Maximum active power usage is the sum of ICC and IPP. 4. Not 100% tested.
22
AM28F010A
25
20
ICC Active in mA
15
10 55C 0C 25C 70C 125C
5
0 0 1 2 3 4 5 6 Frequency in MHz 7 8 9 10 11 12
16778D-15
Figure 7.
AM28F010A--Average ICC Active vs. Frequency VCC = 5.5 V, Addressing Pattern = Minmax Data Pattern = Checkerboard
TEST CONDITIONS
5.0 V
Table 6.
Test Condition
Test Specifications
-70 All others 1 TTL gate 30 10 0.0-3.0 1.5 1.5 0.45-2.4 0.8, 2.0 0.8, 2.0 100 pF ns V V V Unit
Device Under Test CL 6.2 k
2.7 k
Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels
Note: Diodes are IN3064 or equivalent
16778D-16
Output timing measurement reference levels
Figure 8.
Test Setup
AM28F010A
23
SWITCHING TEST WAVEFORMS
2.4 V 2.0 V Test Points 0.8 V 0.45 V Input Output 0.8 V 0V Input Output 2.0 V 1.5 V Test Points 1.5 V 3V
AC Testing (all speed options except -70): Inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0". Input pulse rise and fall times are 10 ns.
AC Testing for -70 devices: Inputs are driven at 3.0 V for a logic "1" and 0 V for a logic "0". Input pulse rise and fall times are 10 ns.
16778D-17
SWITCHING CHARACTERISTICS over operating range, unless otherwise specified AC Characteristics--Read-Only Operations
Parameter Symbols JEDEC tAVAV tELQV tAVQV tGLQV tELQX tEHQZ tGLQX tGHQZ tAXQX tVCS Standard Parameter Description tRC tCE tACC tOE tLZ tDF tOLZ tDF tOH Read Cycle Time (Note 3) Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z (Note 3) Chip Disable to Output in High Z (Note 1) Output Enable to Output in Low Z (Note 3) Output Disable to Output in High Z (Note 3) Output Hold Time From First Address, CE#, or OE# change (Note 3) VCC Set-up Time to Valid Read (Note 3) Min Max Max Max Min Max Min Max Min Min -70 70 70 70 35 0 20 0 20 0 50 AM28F010A Speed Options -90 90 90 90 35 0 20 0 20 0 50 -120 120 120 120 50 0 30 0 30 0 50 -150 150 150 150 55 0 35 0 35 0 50 -200 200 200 200 55 0 35 0 35 0 50 Unit ns ns ns ns ns ns ns ns ns ns
Notes: 1. Guaranteed by design; not tested. 2. Not 100% tested.
24
AM28F010A
AC Characteristics--Write (Erase/Program) Operations
Parameter Symbols JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tOEH tGHWL tELWLE tWHEH tWLWH tWHWL tWHWH3 tWHWH4 tVPEL tVCS tVPPR tVPPF tLKO tCSE tCH tWP tWPH Standard tWC tAS tAH tDS tDH Description Write Cycle Time (Note 4) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Hold Time for Embedded Algorithm only Read Recovery TIme Before Write CE# Embedded Algorithm Setup TIme CE# Hold TIme Write Pulse Width Write Pulse Width High Embedded Program Operation (Note 2) Embedded Erase Operation (Note 3) VPP Setup Time to Chip Enable Low (Note 4) VCC Setup TIme (Note 4) VPP Rise Time (Note 4) 90% VPPH VPP Fall Time (Note 4) 90% VPPL VCC < VLKO to Reset (Note 4) Min Min Min Min Min Min Min Min Min Min Min Min Typ Min Min Min Min Min -70 70 0 45 45 10 10 0 20 0 45 20 14 5 100 50 500 500 100 AM28F010A Speed Options -90 90 0 45 45 10 10 0 20 0 45 20 14 5 100 50 500 500 100 -120 120 0 50 50 10 10 0 20 0 50 20 14 5 100 50 500 500 100 -150 150 0 60 50 10 10 0 20 0 60 20 14 5 100 50 500 500 100 -200 200 0 75 50 10 10 0 20 0 60 20 14 5 100 50 500 500 100 Unit ns ns ns ns ns ns ns ns ns ns ns s sec ns s ns ns ns
Notes: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read Only operations. 2. Embedded Program Operation of 14 s consists of 10 s program pulse and 4 s write recovery before read. This is the minimum time for one pass through the programming algorithm. 3. Embedded Erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a typical time for one embedded erase operation. 4. Not 100% tested.
AM28F010A
25
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
SWITCHING WAVEFORMS
Power-up, Standby Addresses Device and Address Selection Outputs Enabled Data Valid Standby, Power-down
Addresses Stable tAVAV (tRC)
CE# (E#) tEHQZ (tDF) OE# (G#) tWHGL tGHQZ (tDF) tGLQV (tOE) tELQV (tCE) tGLQX (tOLZ) tVCS Data (DQ) tAVQV (tACC) 5.0 V VCC 0V High Z tELQX (tLZ) Output Valid tAXQX (tOH) High Z
WE# (W#)
16778D-18
Figure 9.
AC Waveforms for Read Operations
26
AM28F010A
SWITCHING WAVEFORMS
Embedded Erase Setup Addresses tWC CE# tGHWL OE# tWP WE# tCSE Data tVCS VCC tWPH tDH 30h tDS tCE 30h DQ7# DQ7# tOH tOE tDF tWHWH3 OR 4 tAS tAH tRC Embedded Erase Data# Polling Read
Erase
Standby
VPP tVPEL
16778D-19
Note: DQ7# is the complement of the data written to the device.
Figure 10.
AC Waveforms for Embedded Erase Operation
AM28F010A
27
SWITCHING WAVEFORMS
Embedded Program Setup Addresses tWC CE# tGHWL OE# tWHWH3 OR 4 WE# tCSE tDH Data tVCS tDS VCC tCE tOH tWP tWPH DIN DQ7# DQ7# DOUT tDF Embedded Program PA tAS tAH Data# Polling PA tRC Read
tOE
50h
VPP tVPEL
16778D-20
Notes: DIN is data input to the device. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
Figure 11.
AC Waveforms for Embedded Programming Operation
28
AM28F010A
AC Characteristics--Write (Erase/Program) Operations Alternate CE# Controlled Writes
Parameter Symbols JEDEC tAVAV tAVEL tELAX tDVEH tEHDX tOEH tGHEL tWLEL tEHWK tELEH tEHEL tEHEH3 tEHEH4 tVPEL tVCS tVPPR tVPPF tLKO tWS tWH tCP tCPH Standard tWC tAS tAH tDS tDH Description Write Cycle Time (Note 4) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Hold Time for Embedded Algorithm only Read Recovery Time Before Write WE# Setup Time by CE# CE# Hold Time Write Pulse Width Write Pulse Width High Embedded Program Operation (Note 2) Embedded Erase Operation (Note 2) VPP Setup Time to Chip Enable Low (Note 3) VCC Setup Time (Note 3) VPP Rise Time (Note 3) 90% VPPH VPP Fall Time (Note 3) 90% VPPL VCC < VLKO to Reset (Note 3) Min Min Min Min Min Min Min Min Min Min Min Min Typ Min Min Min Min Min -70 70 0 45 45 10 10 0 0 0 65 20 14 5 100 50 500 500 100 AM28F010A Speed Options -90 90 0 45 45 10 10 0 0 0 65 20 14 5 100 50 500 500 100 -120 120 0 50 50 10 10 0 0 0 70 20 14 5 100 50 500 500 100 -150 150 0 60 50 10 10 0 0 0 80 20 14 5 100 50 500 500 100 -200 200 0 75 50 10 10 0 0 0 80 20 14 5 100 50 500 500 100 Unit ns ns ns ns ns ns ns ns ns ns ns s sec ns s ns ns ns
Notes: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read Only operations. 2. Embedded Program Operation of 14 s consists of 10 s program pulse and 4 s write recovery before read. This is the minimum time for one pass through the programming algorithm. 3. Embedded erase operation of 5 sec consists of 4 sec array pre-programming time and one sec array erase time. This is a typical time for one embedded erase operation. 4. Not 100% tested.
AM28F010A
29
SWITCHING WAVEFORMS
Embedded Program Setup Addresses tWC CE# Embedded Program PA tAS tAH tGHEL OE# tCPH tCP WE#
Data# Polling PA
tEHEH3 OR 4
tWS Data 50h tDS VCC
tDH DIN DQ7# DQ7 DOUT
VPP
tVPEL
16778D-21
Notes: DIN is data input to the device. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
Figure 12.
AC Waveforms for Embedded Programming Operation Using CE# Controlled Writes
30
AM28F010A
ERASE AND PROGRAMMING PERFORMANCE
Limits Parameter Chip Erase Time Chip Programming Time Write/Erase Cycles Byte Programming Time 100,000 14 96 (Note 3) Min Typ (Note 1) 1 2 Max (Note 2) 10 12.5 Unit sec sec Cycles s ms Comments Excludes 00h programming prior to erasure Excludes system-level overhead
Notes: 1. 25C, 12 V VPP. 2. Maximum time specified is lower than worst case. Worst case is derived from the embedded algorithm internal counter which allows for a maximum 6000 pulses for both program and erase operations. Typical worst case for program and erase is significantly less than the actual device limit. 3. Typical worst case = 84 s. DQ5 = "1" only after a byte takes longer than 96 ms to program.
LATCHUP CHARACTERISTICS
Parameter Input Voltage with respect to VSS on all pins except I/O pins (Including A9 and VPP) Input Voltage with respect to VSS on all pins I/O pins Current Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time. Min -1.0 V -1.0 V -100 mA Max 13.5 V VCC + 1.0 V +100 mA
PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance VPP Input Capacitance VIN = 0 VOUT = 0 VPP = 0 Test Conditions Typ 8 8 8 Max 10 12 12 Unit pF pF pF
Note: Sampled, not 100% tested. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
AM28F010A
31
PHYSICAL DIMENSIONS PD032--32-Pin Plastic DIP (measured in inches)
1.640 1.670 32 17 .530 .580 16 .045 .065 .140 .225 .005 MIN 0 10 .630 .700 .009 .015
.600 .625
Pin 1 I.D.
SEATING PLANE .120 .160 .090 .110 .016 .022 .015 .060
16-038-S_AG PD 032 EC75 5-28-97 lv
PL032--32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485 .495 .009 .015 .125 .140 .080 .095 SEATING PLANE .400 REF. .013 .021 .026 .032 TOP VIEW .050 REF. .490 .530 .042 .056
.447 .453
.585 .595 .547 .553
Pin 1 I.D.
SIDE VIEW
16-038FPO-5 PL 032 DA79 6-28-94 ae
32
AM28F010A
PHYSICAL DIMENSIONS TS032--32-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95 1.05 Pin 1 I.D. 1
7.90 8.10
0.50 BSC
18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21
0.05 0.15
1.20 MAX 0 5 0.50 0.70
16-038-TSOP-2 TS 032 DA95 3-25-97 lv
33
AM28F010A
PHYSICAL DIMENSIONS TSR032--32-Pin Reversed Thin Small Outline Package (measured in millimeters)
0.95 1.05 Pin 1 I.D. 1
7.90 8.10
0.50 BSC
18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21
0.05 0.15
1.20 MAX 0 5 0.50 0.70
16-038-TSOP-2 TSR032 DA95 3-25-97 lv
AM28F010A
34
DATA SHEET REVISION SUMMARY FOR AM28F010A Revision C+1
Distinctive Characteristics:
AC Characteristics:
Write/Erase/Program Operations, Alternate CE# Controlled Writes: Added the -70 column. Deleted -95 and -250 speed options.
Switching Test Waveforms: In the 3.0 V waveform caption, changed -95 to -70.
High Performance: The fastest speed option available is now 70 ns.
General Description: Paragraph 2: Changed fastest speed option to 70 ns. Product Selector Guide: Added -70, deleted -95 and -250 speed options. Ordering Information, Standard Products: The -70 speed option is now listed in the example.
Revision D
Matched formatting to other current data sheets.
Revision D+1
Programming In A PROM Programmer: Deleted the paragraph "(Refer to the AUTO SELECT paragraph in the ERASE, PROGRAM, and READ MODE section for programming the Flash memory device in-system)."
Valid Combinations: Added -70, deleted -95 and -250 combinations.
Operating Ranges:
Revision D+2
General Description
VCC Supply Voltages: Added -70, deleted -95 and -250 speed options in the list.
AC Characteristics:
Read Only Operations Characteristics: Added the -70 column and test conditions. Deleted -95 and -250 speed options.
Embedded Program: Changed "The typical room temperature programming time of this device is four seconds." to "The typical room temperature programming time of this device is two seconds."
Trademarks
Copyright (c) 1998 Advanced Micro Devices, Inc. All rights reserved. ExpressFlash is a trademark of Advanced Micro Devices, Inc. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
35
AM28F010A

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